发明名称 |
SAVING POWER WHEN IN OR TRANSITIONING TO A STATIC MODE OF A PROCESSOR |
摘要 |
A method for reducing power utilized by a processor including the steps of determining that a processor is transitioning from a computing mode to a mode is which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.
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申请公布号 |
US2011107131(A1) |
申请公布日期 |
2011.05.05 |
申请号 |
US20110987423 |
申请日期 |
2011.01.10 |
申请人 |
READ ANDREW;HALEPETE SAMEER;KLAYMAN KEITH |
发明人 |
READ ANDREW;HALEPETE SAMEER;KLAYMAN KEITH |
分类号 |
G06F1/32;G06F1/26 |
主分类号 |
G06F1/32 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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