发明名称 TIERED SCHEMATIC-DRIVEN LAYOUT SYNCHRONIZATION IN ELECTRONIC DESIGN AUTOMATION
摘要 Some embodiments provide a system that facilitates the creation of a layout from a schematic in an electronic design automation (EDA) application. During operation, the system performs a tiered comparison of the schematic and the layout. The tiered comparison includes a first tier that compares labels in the schematic and the layout. The tiered comparison also includes a second tier that compares first-level connectivity in the schematic and the layout. The tiered comparison further includes a third tier that determines a graph isomorphism between the schematic and the layout. After the tiered comparison is completed, the system provides a result of the tiered comparison to a user of the EDA application. Finally, the system enables repairs of mismatches in the result by the user through a graphical user interface (GUI) associated with the EDA application.
申请公布号 US2011107281(A1) 申请公布日期 2011.05.05
申请号 US20090610054 申请日期 2009.10.30
申请人 SYNOPSYS, INC. 发明人 SUN WERN-JIEH;CHUN HAICHUN;MAYER ERNST W.;WOOLHISER GREG;KARLCUT KULDEEP
分类号 G06F17/50 主分类号 G06F17/50
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