发明名称 Datenverarbeitungssystem
摘要 One data processor (101) is provided with an interface means (119) for realizing connection with the other data processor (100), this interface means is provided with a function for connecting the other data processor as a bus master to an internal bus (108) of one data processor, and the relevant other data processor is capable of operating in direct peripheral functions memory mapped to the internal bus from an external side via said interface means. Accordingly, the data processor can utilize the peripheral functions of the other data processor without intermission of the program being executed. In short, one data processor can use in common the peripheral resources of the other data processor. <IMAGE>
申请公布号 DE60144303(D1) 申请公布日期 2011.05.05
申请号 DE2001644303 申请日期 2001.10.24
申请人 RENESAS ELECTRONICS CORP. 发明人 NISHIMOTO, JUNICHI;NAKAZAWA, TAKUICHIRO;YAMADA, KOJI;HATTORI, TOSHIHIRO
分类号 G06F9/44;G06F15/177;G06F1/32;G06F9/445;G06F11/00;G06F12/06;G06F13/10;G06F13/36;G06F13/38;G06F13/40 主分类号 G06F9/44
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