发明名称 Semiconductor chip and wafer stack package using the same and method of manufacturing the same
摘要 <p>PURPOSE: A semiconductor chip, wafer stack package using the same, and manufacturing method thereof are provided to insert the other end of a second conductive plug of a lower substrate into the second via of an upper substrate, thereby electrically connecting the first conductive plug of the lower substrate with the second conductive plug of the upper substrate. CONSTITUTION: A first via hole(120a) is formed on the frontal side of a substrate(110). A first conductive plug(150a) is formed using a first conductive material in the first via hole. A second conductive plug(150b) is formed using a second conductive material on the first conductive plug. The back side of the substrate is wrapped. A second via hole(120b) in parallel with the first via hole is formed on the back side of the wrapped substrate.</p>
申请公布号 KR20110046126(A) 申请公布日期 2011.05.04
申请号 KR20090102980 申请日期 2009.10.28
申请人 发明人
分类号 H01L23/12 主分类号 H01L23/12
代理机构 代理人
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