发明名称 System and method for generating a configurable processor supporting a user-defined plurality of instruction sizes
摘要 A processor generation system includes the ability to describe processors with three instruction sizes. In one example implementation, instructions can be 16-, 24- and 64-bits. This enables a new range of architectures that can exploit parallelism in architectures. In particular, this enables the generation of VLIW architectures. According to another aspect, the processor generator allows a designer to add a configurable number of load/store units to the processor. In order to accommodate multiple load/store units, local memories connected to the processor can have multiple read and write ports (one for each load/store unit). This further allows the local memories to be connected in any arbitrary connection topology. Connection box hardware is automatically generated that provides an interface between the load/store units and the local memories based on the configuration.
申请公布号 US7937559(B1) 申请公布日期 2011.05.03
申请号 US20070761322 申请日期 2007.06.11
申请人 TENSILICA, INC. 发明人 PARAMESWAR AKILESH;FISKE JAMES ALEXANDER STUART;GONZALEZ RICARDO E.
分类号 G06F9/00 主分类号 G06F9/00
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