发明名称 |
Alias-locked loop frequency synthesizer using a regenerative sampling latch |
摘要 |
A frequency synthesis phase-locked loop architecture using a regenerative sampling latch is described. The frequency divider typically employed in the feedback path of a frequency synthesis phase-locked loop is replaced by a regenerative sampling latch with a binary output. The regenerative sampling latch subsamples the frequency synthesizer output to produce a low-frequency aliased signal that can be processed further or directly used to lock the phase-locked loop. This architecture is referred to as an alias-locked loop. The relaxed constraints on the regenerative sampling latch make it possible to create high-speed frequency synthesizer phase-locked loops without the suffering the limitations imposed by traditional dividers connected directly to the oscillator output.
|
申请公布号 |
US7936192(B2) |
申请公布日期 |
2011.05.03 |
申请号 |
US20090467254 |
申请日期 |
2009.05.15 |
申请人 |
VAN DEN BERG LEENDERT JAN;ELLIOTT DUNCAN GEORGE |
发明人 |
VAN DEN BERG LEENDERT JAN;ELLIOTT DUNCAN GEORGE |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|