发明名称 PACKAGE FOR HIGH POWER INTEGRATED CIRCUITS AND METHOD FOR FORMING
摘要 A method for packaging an integrated circuit comprises the steps of: providing a ground plane, the ground plane having a recessed area shaped to receive an integrated circuit die, wherein the integrated circuit die having a first surface with active circuitry, a second surface, and an edge generally orthogonal to the first and second surfaces; attaching the second surface of the integrated circuit die to a bottom of the recessed area with a thermally conductive adhesive; filling a space between the edge of the integrated circuit die and a side of the recessed area with a fill material; forming an insulating layer on the ground plane and the first surface of the integrated circuit die; patterning the insulating layer to expose contacts on the first surface of the integrated circuit die; and plating electrical conductors on the insulating layer and the contacts.
申请公布号 US2011095416(A1) 申请公布日期 2011.04.28
申请号 US20090606585 申请日期 2009.10.27
申请人 SARIHAN VUAY 发明人 SARIHAN VUAY
分类号 H01L23/498;H01L21/60 主分类号 H01L23/498
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