| 摘要 |
<p>Disclosed is a semiconductor device layout wherein gate length variance due to optical proximity effects can be reliably suppressed and layout can be freely designed. The gate patterns (G1, G2, G3) of a cell (C1) are disposed at a same pitch, and the positions of the end portions (e1, e2, e3) of the gate patterns are same in the Y direction and the widths thereof are same in the X direction. The gate pattern (G4) of the cell (C2) has a protruding section (4b) which extends in the Y direction toward the cell (C1), and the protruding section (4b) configures facing end portions (eo1, eo2, eo3). The facing end portions (eo1, eo2, eo3) are disposed at the same pitch, at which the gate patterns (G1, G2, G3) are disposed, and the positions of the end portions are same in the Y direction and the widths thereof are same in the X direction.</p> |
