发明名称 Error control coding for single error correction and double error detection
摘要 An error correction coding is provided that generates P bits of check data from K M-bit words of payload data. The P bits of check data include an address field A, a bit error indicating field E and an auxiliary field P−(E+A). The address field encodes a set of error addresses which has a cardinality equal to the bit size K of the payload data and providing a one-to-one mapping between values of the address field and the locations of a single bit error within the payload data. The bit error indicating field indicates if a bit error is present. The auxiliary field is a minimum size bit vector such that together with the address field and the bit area indicating field it provides a checksum for a systematic code for the payload data with a minimum Hamming distance serving to provide either single error correction capability or single error correction and double error detection capability.
申请公布号 US2011099451(A1) 申请公布日期 2011.04.28
申请号 US20090588665 申请日期 2009.10.22
申请人 ARM LIMITED 发明人 WEZELENBURG MARTINUS CORNELIS;CONWAY THOMAS KELSHAW
分类号 H03M13/29;G06F11/10 主分类号 H03M13/29
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