| 摘要 |
Provided are a cache memory and a control method thereof, by which electric power consumption can be reduced without reducing a cache hit ratio. A CAM sub-tag address extraction unit (22a) extracts a CAM sub-tag address from a tag address. A SRAM sub-tag address extraction unit (22b) extracts a SRAM sub-tag address from the tag address. A CAM (51) retrieves data by comparing CAM sub-tag addresses. A comparison retrieval unit (71) retrieves data by comparing the extracted SRAM sub-tag address and the SRAM sub-tag address stored in the SRAM, with respect to recently read out first generation data among the data of the retrieved tag address. An output unit (72) outputs, as a response to a request, the first generation data which is retrieved by the comparison retrieval unit (71) and stored in association with the SRAM sub-tag address. The method can be applied to a cache memory. |
