发明名称 INSTRUCTION SIZE REDUCTION DEVICE
摘要 PROBLEM TO BE SOLVED: To reduce an instruction size by executing a flag control instruction that is an instruction of some sort based on a flag group in a short instruction length of byte, in an instruction size reduction device. SOLUTION: The instruction size reduction device includes: a CPU 1; a memory 2 storing an instruction of the CPU 1; and a flag group storage means 4 storing two or more flags. The instruction size reduction device also includes a flag limitation means 7 limiting and selecting a specific flag from a flag group in the flag group storage means 4. The CPU 1 inputs the flag limited and selected by the flag limitation means 7, and executes an instruction based on information of the specific flag. By controlling the flag limitation means 7, a limitation flag group 9 obtained by selecting the flags of the flag group storage means 4 is created, and the number of the flags entering the CPU 1 is restricted. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011086234(A) 申请公布日期 2011.04.28
申请号 JP20090240335 申请日期 2009.10.19
申请人 PANASONIC CORP 发明人 FURUKAWA KAZUYA
分类号 G06F9/32 主分类号 G06F9/32
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