| 摘要 |
PROBLEM TO BE SOLVED: To provide a CMOS integrated circuit, which that has a plurality of row region portions 2 arranged longitudinally and laterally and includes a plurality of wiring layers and in which interlayer wiring lines are connected via a via, capable of having higher wiring efficiency, a smaller chip size, and improved working speed by improving the patterns of a power source and a ground. SOLUTION: A power supply pattern A10 and a ground pattern A20 are formed longitudinally of a wiring layer, having a thick film thickness at a lateral row region portion 2. In a region where the power supply pattern A10 is formed longitudinally, a power supply pattern 11 of the row region portion 2 is separated to the right and the left in a formation region of the longitudinal power supply pattern A10, and is connected to the longitudinal power supply pattern A10 via a via 30, respectively. A longitudinal ground pattern B201 is formed of the same layer with a ground pattern 21 of the row region portion 2 between the separated power supply patterns 11 of the row region portion 2, and connected directly to the ground pattern 21 of the row region portion 2. COPYRIGHT: (C)2011,JPO&INPIT
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