发明名称 Integrated circuit with improved test capability via reduced pin count
摘要 An integrated circuit that supports testing of multiple pads via a subset of these pads includes at least two sections. Each section has multiple pads and multiple test access circuits coupled to these pads. For each section, one pad is designated as a primary pad and the remaining pads are designated as secondary pads. For each section, the test access circuits couple the secondary pads to the primary pad such that all of the pads in the section can be tested by probing just the primary pad. Each test access circuit may be implemented with a simple switch. A controller generates a set of control signals for the test access circuits in all sections. These control signals enable and disable the test access circuits such that all of the sections can be tested in parallel, and the pads in each section can be tested in a sequential order.
申请公布号 US7932736(B2) 申请公布日期 2011.04.26
申请号 US20100704717 申请日期 2010.02.12
申请人 QUALCOMM INCORPORATED 发明人 VARADARAJAN SRINIVAS;LAISNE MICHAEL;BHATTAGIRI RAGHUNATH R.;SAMMULI ARVID G.
分类号 G01R31/3187 主分类号 G01R31/3187
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