发明名称 Method and apparatus for supporting delay analysis, and computer product
摘要 A delay distribution of a partial path that passes through a node to which a plurality of signals is input and for which an estimation in a statistical MAX is predicted to be large, that is present on a critical path having large influence on a circuit delay, and that has high possibility of improving the circuit delay, among nodes in a circuit graph is calculated by the Monte Carlo simulation instead of the block based simulation, thereby increasing speed and accuracy of delay analysis.
申请公布号 US7934182(B2) 申请公布日期 2011.04.26
申请号 US20080193431 申请日期 2008.08.18
申请人 FUJITSU LIMITED 发明人 NITTA IZUMI;HOMMA KATSUMI;SHIBUYA TOSHIYUKI
分类号 G06F17/50 主分类号 G06F17/50
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