发明名称 Reduction of package height in a stacked die configuration
摘要 A method and structure for reducing the size of semiconductor package is disclosed. In one example embodiment, a method for stacking dies of a semiconductor package includes forming a set of insulated bonding wires between respective bonding pads of a first semiconductor integrated circuit die and a conductive layer electrically detached from the respective bonding pads, applying an adhesive material on a top surface of the first semiconductor integrated circuit die, and securing a second semiconductor integrated circuit die one the top surface of the first semiconductor integrated circuit die with the adhesive material.
申请公布号 US7932131(B2) 申请公布日期 2011.04.26
申请号 US20070983041 申请日期 2007.11.05
申请人 SPANSION LLC 发明人 FOONG SALLY;GUAN KEVIN;LEE CHANGHAK;CHIN LAI NGUK;TZIAT ROYCE YEOH KAO;HO FOONG YUE
分类号 H01L21/00;H01L23/02;H01L23/52 主分类号 H01L21/00
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