发明名称 |
Data processing apparatus which prevents data overflow and underflow |
摘要 |
A data processing apparatus constitutes a low-cost audio/video data transmission and reception system. A reception buffer monitoring circuit 21 monitors the size of receiver data being accumulated in a reception buffer 6. When the size of accumulated data is found to become higher than a high threshold, the circuit 21 causes a reception clock generation circuit 8 to generate a reception clock with a higher frequency. When the accumulated data size becomes lower than a low threshold, the reception clock is generated with a lower frequency. Based on the reception clock fed from the reception clock generation circuit 8, an audio/video decoder 7 decodes the audio/video data coming from the reception buffer 6. The data processing apparatus applies advantageously to a television transmission and reception system for transmitting and receiving TV broadcast signals.
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申请公布号 |
US7933949(B2) |
申请公布日期 |
2011.04.26 |
申请号 |
US20080113431 |
申请日期 |
2008.05.01 |
申请人 |
SONY CORPORATION |
发明人 |
YOSHIDA HIDEKI;SATO JIN;IKEDA KAZUYUKI;NORIZUKI TAKASHI;SAKUSABE KENICHI;KAWAGUCHI DAISUKE;YOSHIKAWA MUNEHIRO |
分类号 |
G06F15/16;H04B14/04;H04L7/00;H04L13/08;H04N5/04;H04N5/38;H04N5/44;H04N7/26 |
主分类号 |
G06F15/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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