发明名称 MEMORY TEST DEVICE
摘要 PROBLEM TO BE SOLVED: To reduce scanning time of a buffer memory 14 in redundancy processing. SOLUTION: A memory test device includes: a determining part for determining quality of a DUT; a fail memory for storing fail data output from the determining part; a format converting part for converting a data format of the fail data stored in the fail memory; a buffer memory for storing the fail data converted by the format converting part; and a redundancy operating part for performing redundancy processing for each IO of the DUT by scanning the buffer memory for each address. The format converting part converts the data format of the fail data so that the fail data of a plurality of addresses in one IO of the DUT is stored on one address in the buffer memory, from the data format in which the fail data of one address in each IO of the DUT is stored on one address in the fail memory. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011081856(A) 申请公布日期 2011.04.21
申请号 JP20090231529 申请日期 2009.10.05
申请人 YOKOGAWA ELECTRIC CORP 发明人 KIMURA TAKAHIRO
分类号 G11C29/44 主分类号 G11C29/44
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