| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide an integrated circuit having silicon on a stress liner, and its manufacturing method. <P>SOLUTION: The method comprises a step of preparing a semiconductor substrate comprising an outer semiconductor layer and an embedded sacrifice layer under the outer semiconductor layer, and a step of removing at least a portion of the embedded sacrifice layer to form a void within the semiconductor substrate. The method further comprises a step of depositing a material in the void to form the stress liner, and a step of forming a transistor on the outer semiconductor layer of the semiconductor substrate. The outer semiconductor layer separates the transistor from the stress liner. The semiconductor substrate includes isolation regions, and the removing step includes a step of forming recesses in the isolation regions, and a step of removing at least a portion of the embedded sacrifice layer via these recesses. The depositing step includes a step of depositing a material in the void via the recesses 46. End caps 60 are formed in the recesses 46 contacting with ends of the stress liner. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
