发明名称 Delay Line Calibration Mechanism and Related Multi-Clock Signal Generator
摘要 A delay line calibration mechanism includes a first delay line, a second delay line, a phase detector, and a controller. The first delay line receives a first pulse and a first delay selection signal, and delays the first pulse for a first delay period according to the first delay selection signal to output a first delayed pulse. The second delay line receives a second pulse and a second delay selection signal, and delays the second pulse for a second delay period according to the second delay selection signal to output a second delayed pulse. The phase detector generates a phase difference signal indicating the phase difference between the first delayed pulse and the second delayed pulse by comparing the first delayed pulse and the second delayed pulse. The controller generates the second delay selection signal, and generates the first delay selection signal according to the phase difference signal.
申请公布号 US2011089985(A1) 申请公布日期 2011.04.21
申请号 US20100980359 申请日期 2010.12.29
申请人 KAO HONG-SING;YANG MENG-TA;HSU TSE-HSIANG 发明人 KAO HONG-SING;YANG MENG-TA;HSU TSE-HSIANG
分类号 H03L7/00 主分类号 H03L7/00
代理机构 代理人
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