| 摘要 |
PROBLEM TO BE SOLVED: To provide a P-channel semiconductor device having an enhanced NBTI (negative bias temperature instability). SOLUTION: The semiconductor includes a control electrode containing at least a gate dielectric layer SiO on a semiconductor P-channel layer SiGe, wherein the gate dielectric layer SiO has a defect level E<SB>t</SB>, which decreases exponentially as function of energy, from the band edges of the adjacent layer (being the semiconductor P-channel layer SiGe, or optionally a capping layer Si) toward the center of the band gap of the layer. COPYRIGHT: (C)2011,JPO&INPIT |
