发明名称 Multilayer wiring, method for placing dummy wiring in multilayer wiring, semiconductor device, and semiconductor device manufacturing method
摘要 A multilayer wiring in which plural metal wirings and plural interlayer insulating films are layered, each interlayer insulating film being planarized each time formed, is divided into plural regions. The percentage of an area occupied by each of the metal wirings within each region is obtained for each of the metal wirings. An integral percentage is obtained per region by integrating, the percentages. The integral percentages are used to calculate the relative positional relationship of upper surfaces of the interlayer insulating films of plural regions, from the relative values of the integral percentages obtained beforehand and relative positions of the upper surfaces. In regions where the upper surface is of a height lower than a predetermined value, a dummy wiring is disposed, and in regions where the upper surface is of a height equal to or greater than the predetermined value, a dummy wiring is not disposed.
申请公布号 US2011089569(A1) 申请公布日期 2011.04.21
申请号 US20100801551 申请日期 2010.06.14
申请人 OKI SEMICONDUCTOR CO., LTD. 发明人 ASAKAWA KAZUHIKO
分类号 H01L23/52;H01L21/768 主分类号 H01L23/52
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