发明名称 SIMULATION METHOD, SYSTEM, AND PROGRAM
摘要 <p>Provided is a V-PILS by which reproducibility of a simulation operation can be achieved while reasonably maintaining a operation speed. A peripheral scheduler starts concurrent operation of all peripheral emulators, identifies a peripheral emulator (peripheral P) which is scheduled to reach a separation of a process earliest on the basis of the process separation time of the set respective peripheral emulators, executes each processor emulator and each plant simulator until the separation time, and synchronizes data between the peripheral P and the processor emulator and the peripheral P and the plant simulator.</p>
申请公布号 WO2011046089(A1) 申请公布日期 2011.04.21
申请号 WO2010JP67772 申请日期 2010.10.08
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION;SHIMIZU SHUICHI;KOMATSU HIDEAKI;KAJITANI KOHICHI 发明人 SHIMIZU SHUICHI;KOMATSU HIDEAKI;KAJITANI KOHICHI
分类号 G06F11/28 主分类号 G06F11/28
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