发明名称 SEMICONDUCTOR WAFER HAVING SCRIBE LANE ALIGNMENT MARKS FOR REDUCING CRACK PROPAGATION
摘要 A wafer including at least a first die and at least a second die, wherein the first die and the second die are separated from each other by an area located between the first die and the second die, is provided. The wafer further includes an alignment mark group used for aligning the wafer to a tool used for patterning the wafer. The alignment mark group is located entirely within the area between the first die and the second die and the alignment mark group includes a plurality of alignment lines, and wherein each line of the plurality of alignment lines is formed using a plurality of segments separated from each other by a plurality of gaps filled with an insulating material.
申请公布号 US2011089581(A1) 申请公布日期 2011.04.21
申请号 US20090581549 申请日期 2009.10.19
申请人 POL VICTOR;FU CHONG-CHENG 发明人 POL VICTOR;FU CHONG-CHENG
分类号 H01L23/544 主分类号 H01L23/544
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