| 摘要 |
<p>An apparatus and associated method are provided for decoding of block wise coded video pictures. Implementing a de-blocking filter algorithm or the like in a single instruction multiple data (SIMD) environment, especially for processors with 128-bit vector registers. Parallelism between the SIMD and the register size fits the macroblock size disclosed in the H.264 and MPEG-4 standards is exploited by using transpositions and transformations of luminance and chrominance macroblocks in vertical de-blocking filter operations.</p> |
