发明名称 |
Processor reduction unit for accumulation of multiple operands with or without saturation |
摘要 |
<p>A processor having a reduction unit that sums m input operands plus an accumulator value, with the option of saturating after each addition or wrapping around the result of each addition. The reduction unit also allows the m input operands to be subtracted from the accumulator value by simply inverting the bits of the input operands and setting a carry into each of a plurality of reduction adders to one. The reduction unit can be used in conjunction with m parallel multipliers to quickly perform dot products and other vector operations with either saturating or wrap-around arithmetic.
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申请公布号 |
EP2290525(A3) |
申请公布日期 |
2011.04.20 |
申请号 |
EP20100011563 |
申请日期 |
2004.05.07 |
申请人 |
ASPEN ACQUISITION CORPORATION |
发明人 |
SCHULTE, MICHAEL J.;BALZOLA, PABLO I.;HOKENEK, ERDEM;GLOSSNER, JOHN C. |
分类号 |
G06F7/38;G06F7/00;G06F7/544;G06F9/302;G06F9/38 |
主分类号 |
G06F7/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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