LATENCY CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

摘要

PURPOSE: A latency circuit and a semiconductor device including the same are provided to stably generate a latency signal in regardless of the operation of a high frequency and PVT variation. CONSTITUTION: A latency control block(110) delays a delayed synchronous signal. The latency control block generates a plurality of first control clocks. The latency control block generates a second control clock. The second control clock has a certain margin of a read command. An inside read command generator(120) samples the second control clock. The inside read command generator generates an inside read command. A latency signal generating unit(130) generates a latency signal.