| 摘要 |
A two-dimensional adder architecture which can receive various block (matrix or array) sizes up to 16 by 16 and sums all the elements in the matrix/array. The architecture comprises first and second stages 604, 608 of one-dimensional adder systems (adder trees) [Fig. 1] where each system comprises an input routing network [Fig. 1; 108], a plurality of adder units [Fig. 1; 112] and an output routing network [Fig. 1; 116]. The number of adder systems in each stage may be sixteen, and each system may have fifteen adder units. The outputs of the first stage comprise the inputs of the second stage 606. The input and output routing networks utilise multiplexers to handle the various block sizes; the input routing network may comprise 20 two-to-one multiplexers, and the output routing network may comprise 39 two-to-one multiplexers. This architecture may be used to help compute a sum of absolute differences (SAD) between pixels for video processing applications such as block based estimation in video encoders. |
