| 摘要 |
Components of a data processing system, such as processors and memories, communicate over an interconnect 10. Initiators 20-26 send transaction requests to recipients 30-36. Requests transmitted after a barrier request are delivered after the barrier request and requests transmitted before the barrier request are delivered before it. When the barrier request reaches a point 41, 42 in the interconnect where there are divergent paths, the barrier request is duplicated along all the paths. A barrier response is generated from a divergent point when one has been received from all the paths. The interconnect contains blocking circuitry 90, which, on receipt of a barrier request, sends the request to the recipient and then blocks subsequent requests until it receives a response. The interconnect contains clearing circuitry 80, where there are no further divergent paths before the recipient or a blocking circuit, which sends a response when it receives a barrier request. |
