发明名称 Semiconductor packaging method to save interposer
摘要 A semiconductor packaging method without an interposer is revealed. A mother chip is a two-layer structure consisting of a semiconductor layer and an organic layer where a redistribution layer is embedded into the organic layer with a plurality of first terminals and a plurality of second terminals disposed on the redistribution layer and exposed from the organic layer. The mother chip is flip-chip mounted on the substrate. The active surface of the daughter chip is in contact with the organic layer with the bonding pads of the daughter chip bonded to the first terminals. Furthermore, a plurality of electrically connecting components electrically connect the second terminals to the substrate. In the multi-chip stacked package, the interposer can be eliminated with a thinner overall package thickness as well as controlled package warpage.
申请公布号 US7927919(B1) 申请公布日期 2011.04.19
申请号 US20090630623 申请日期 2009.12.03
申请人 POWERTECH TECHNOLOGY INC. 发明人 FAN WEN-JENG;FANG LI-CHIH;IWATA RONALD TAKAO
分类号 H01L21/00 主分类号 H01L21/00
代理机构 代理人
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