发明名称 |
Systems and methods for a PLL-adjusted reference clock |
摘要 |
A system is provided, the system includes a phase-locked loop (PLL) that multiplies a reference clock input to generate a communication link clock signal. The system also includes a transmitter/receiver (TX/RX) module coupled to the PLL, the TX/RX module is configured to transmit and receive data based on the communication link clock signal. The system also includes a divider coupled to the PLL, the divider receives the communication link clock signal and outputs a PLL-adjusted reference clock that approximates the reference clock input. The PLL-adjusted reference clock is used to generate at least one other communication link clock signal.
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申请公布号 |
US7929919(B2) |
申请公布日期 |
2011.04.19 |
申请号 |
US20080237869 |
申请日期 |
2008.09.25 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. |
发明人 |
COPPIN JUSTIN |
分类号 |
H04B1/40;H04B7/00;H04L7/00 |
主分类号 |
H04B1/40 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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