VERZÖGERUNGSUNEMPFINDLICHER ASYNCHRONER SCHALTKREIS MIT VERZÖGERUNGSEINSCHALTSCHALTKREIS

摘要

The circuit has a delay insertion circuit comprising a Muller gate (5) and a set of delay circuits (D1-Dn) connected in series to an output (S0) of the Muller gate between a signal input (S) and a signal output (Sd). Each delay circuit has an output connected to corresponding inputs (M1-Mn) of a multiplexing circuit whose output constitutes an output of the delay insertion circuit. The Muller gate has an input constituting an input of the delay insertion circuit and another input connected to an output (Sn) of the last delay circuit (Dn) through an inverter gate (6).