UMKONFIGURIERBARES ANWEISUNGS-ZELLEN-ARRAY

摘要

A reconfigurable processor architecture, compiler and method of program instruction execution provides reduced cost, short design time, low power consumption and high performance. The processor executes program instructions having datapaths of both dependent and independent program instructions. Simultaneous multithreading is also Interconnects Network supported. The processor has a reconfigurable core (1) with an interconnection network (4) and a heterogeneous array of instruction cells (2) each connected to the interconnection network (4). A decoding module (11) receives configuration instruction (10), each instruction encoding the mapping of one of the datapaths to a circuit of the instruction cells (2). The decoding module (11) decodes each configuration instruction (10) and configures the interconnection network (4) and instruction cells in order to map the datapath to the circuit of the instruction cells and execute the program instructions. A clock module (24) is reconfigurable each clock cycle by the configuration instruction (10). The compiler generates configuration instructions (10) for the processor by identifying the datapaths of both dependent and independent program instructions then mapping them as circuits of the instruction cells (2) using operation chaining.