| 摘要 |
PROBLEM TO BE SOLVED: To reduce the frequency of accesses to a peripheral modules in interruption processing, and to reduce a load factor of a CPU. SOLUTION: An interruption request signal and an interruption data are output from the optional peripheral module to an interruption control circuit 5, when an interrupt event occurs. The interruption control circuit 5 stores the received interruption data into a register 15, and determines the priority of the interruption request signal. Subsequently, the interrupt control circuit 5 transfers a determination result as the interruption request signal via a dedicated wire 17 and the interruption data of the register 15 via a dedicated bus 16 respectively to the CPU 2. The CPU 2 reads out a corresponding interrupt processing function from a ROM 3, based on the input interrupt request signal, when receiving the interruption request, and executes the processing of the interruption data. COPYRIGHT: (C)2011,JPO&INPIT |
