| 摘要 |
A device includes first to N-th (N is an integer of 2 or more) semiconductor chips stacked. These semiconductor chips have substantially the same configuration, and each includes an identification flag memory circuit including first to N-th memory units and a plurality of through electrodes connected to the identification flag memory circuit. Each of the through electrodes is connected to or masked with respect to the corresponding one of the through electrodes of the underlying semiconductor chip, such that an identification flag is stored in n-th (n indicates 1, 2, . . . , and N) memory units of the n-th semiconductor chips sequentially in the stacking order in response to a clock signal input in common to the first to N-th semiconductor chips, and the storage of the identification flag in the N-th memory unit of the N-th semiconductor chip can be detected from the lower side of the first semiconductor chip. |
