| 摘要 |
A static random access memory is disclosed. The SRAM comprises: at least one data line for transferring data to and from the memory and at least one reset line; a plurality of storage cells each being arranged for connection to the at least one data line and the at least one reset line, each storage cell comprising: an asymmetric feedback loop, the feedback loop comprising a first access node for holding a data value when the feedback loop stores the data value and a second access node for holding a complementary version of the data value when the feedback loop stores the data value; an access device for selectively providing a connection between the at least one data line and the first access node; a reset device for selectively providing a connection between the at least one reset line and the second access node; the memory further comprising: data access control circuitry for generating control signals in response to data access requests for independently controlling the access device and the reset device to provide the connections; wherein: the data control circuitry is configured to: generate a data access control signal to trigger the access device to provide the connection between the first access node and the at least one data line in response to a write request to write a predetermined value to the storage cell, and in response to a read request to read a stored value from the storage cell; and generate a reset control signal to trigger the reset device to provide the connection between the at least one reset line and the second access node in response to a write request to write the complementary predetermined value to the storage cell.
|
