| 摘要 |
<p>Disclosed is a semiconductor device using a vertical MOS transistor wherein source parasitic resistance and a back-bias effect can be ignored. The semiconductor device is provided with at least one vertical MOS transistor (1), and the vertical MOS transistor (1) is provided with: a semiconductor post (2); a source region (3) formed on one end of the semiconductor post (2); a source electrode (4); a drain region (5) formed on the other end of the semiconductor post (2); a drain electrode (6); a gate oxide film (7) disposed so as to surround the side surface of the semiconductor post; a gate electrode (8); and a drain parasitic resistance (15). The drain region (6) is composed of an impurity diffused layer (11) formed on a substrate, and the drain parasitic resistance (15) is formed between the impurity diffused layer (11) and the drain electrode (5). In the vertical MOS transistor (1), there is no back-bias effect of showing an increase of a threshold voltage due to an increase of the absolute value of a substrate bias, said back-bias effect being observed in conventional planar MOS transistors.</p> |
