Apparatus and method for annealing of III-V wafers and annealed III-V semiconductor single crystal wafers

摘要

Device for heat-treating III-V semiconductor wafers comprises a wafer carrier with dimensions such that a cover is formed no more than 2 mm above the wafer surface after a wafer has been placed in the carrier. Independent claims are also included for: (1) heat-treating III-V semiconductor wafers divided from as-grown monocrystals with a diameter of at least 100 mm by heat-treating the wafers in a state such that the surface to be treated is either covered directly with a gas-permeable or porous material or is covered with a material (gas-permeable or porous or not) with a spacing of 0-2 mm; (2) heat-treating III-V semiconductor wafers divided from as-grown monocrystals with a diameter of at least 100 mm by heat-treating the wafers in quartz-free heat treatment apparatus comprising at least one wafer carrier after cleaning and etching and before edge-rounding; (3) gallium arsenide semiconductor crystal wafer with a diameter of at least 100 mm and a dislocation density of no more than 10 4> cm -> 2>, where the characteristic breaking strength, corresponding to a 63.2% failure rate (Weibull distribution), is at least 25% greater than that of semi-insulating gallium arsenide (SI GaAs) wafers made from crystal-tempered material; (4) gallium arsenide semiconductor crystal wafer with a diameter of at least 100 mm and a dislocation density of no more than 10 4> cm -> 2>, where the characteristic breaking strength, corresponding to a 63.2% failure rate (Weibull distribution), is more than 1900 MPa.