Scales with single clock phase and reduced dynamic power.

摘要

The flip-flop has a master data locking stage i.e. memory locking block (B2), a slave data locking stage i.e. another memory locking block (B3), and a multiplexer block (B1) receiving the data to be locked in the flip-flop at input. The multiplexer block is controlled by a single clock signal (CP). The memory locking blocks are clocked from respective clock signal phases. The latter memory locking block has a memory stage (BS1) and an inverter (IV1) i.e. metal oxide semiconductor inverter, in input of the memory stage.