发明名称 Validating data using processor instructions
摘要 In one embodiment, the present invention includes a method for determining from a data block in a buffer a number of first operands in a first portion of the buffer and a number of second operands in a second portion of the buffer. Based on these numbers, a cyclic redundancy checksum (CRC) operation may be iteratively performed on the first and second operands to obtain a checksum result. The first and second operands are of a different length, and the checksum operation may be executed using processor instructions corresponding to the different lengths. Other embodiments are described and claimed.
申请公布号 US7925957(B2) 申请公布日期 2011.04.12
申请号 US20060384527 申请日期 2006.03.20
申请人 INTEL CORPORATION 发明人 KING STEVEN R.;BERRY FRANK L.;JOGLEKAR ABHIJEET
分类号 H03M13/00 主分类号 H03M13/00
代理机构 代理人
主权项
地址