发明名称 |
Message-based low latency circuit emulation signal transfer |
摘要 |
Message send and receive blocks are provided to emulation ICs and reconfigurable interconnect ICs of an emulation system to reduce the multiplexed transfer latency of critical emulation signals. Each of a corresponding pair of a message send block and a message receive block is provided with a signal state value inclusion schedule to control operation of the message send and receive blocks. The signal state inclusion schedule calls for some signals within a message to be sent more often than other signals within the message. In some embodiments a parity value is implemented as part the message and included in the signal state inclusion schedule.
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申请公布号 |
US7924845(B2) |
申请公布日期 |
2011.04.12 |
申请号 |
US20030673665 |
申请日期 |
2003.09.30 |
申请人 |
MENTOR GRAPHICS CORPORATION |
发明人 |
DIEHL PHILIPPE;VIEILLOT MARC;QUENNESSON CYRIL;LAURENT GILLES;REBLEWSKI FREDERIC |
分类号 |
H04L12/28;G06F3/00;G06F9/455;G06F11/22;G06F11/26;G06F17/50;H01L25/00;H04L12/56 |
主分类号 |
H04L12/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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