Use of three phase clock in sigma delta modulator to mitigate the quantization noise folding

摘要

A differential sigma delta modulator operates by modulating an input signal by intermittently coupling a reference signal to the input signal using one or more switches controlled by one or more feedback signals and a respective one or more non-overlapping clock signals. The modulated input signal is integrated using an integration capacitor to form an integrated value and the integrated value is compared to a threshold to form the one or more feedback signals. Parasitic capacitance of the one or more switches is initialized to an initial value prior to each intermittent coupling of the reference signal to the input signal using another non-overlapping clock signal.