| 摘要 |
PROBLEM TO BE SOLVED: To easily adjust the center frequency of a PLL (Phase Locked Loop) circuit. SOLUTION: A frequency signal is input to a drive circuit 61 from a frequency signal generating unit 76 in a CPU 50 via a selector circuit 59 and a switch circuit 60. The drive circuit 61 applies a driving voltage of the same frequency as the frequency signal to BLTs 45. A phase difference between the driving voltage and an electric current is found in a PSD (Position Sensitive Detector) circuit 69. The phase different in each frequency is found by gradually changing the frequency of the frequency signal output from the frequency signal generating unit 76. A frequency determining unit 74 compares phase differences for respective frequencies, and determines the frequency of the minimum phase difference as the center frequency in the PLL circuit 64. COPYRIGHT: (C)2011,JPO&INPIT |
