发明名称 CPU INSTRUCTION AND DATA CACHE CORRUPTION PREVENTION SYSTEM
摘要 Various exemplary embodiments relate to a cache corruption prevention system and a related method. A cache memory may contain contents that are susceptible to corruption. A cache controller, with the use of a threshold timer, may employ various operations to flush modified cache contents into a main memory and invalidate cache contents so that they are overwritten. Some operations include periodically flushing and invalidating the whole cache memory, periodically flushing and invalidating modified contents, and periodically flushing and invalidating contents based on the time saved in the cache memory. By overwriting cache contents that might otherwise be constantly stored in the cache memory, the system minimizes the probability of cache contents becoming corrupt. The periodic updating of the main memory may also increase the probability of successfully recovering from potential cache parity errors while still maintaining high performance associated with using a cache memory.
申请公布号 US2011082983(A1) 申请公布日期 2011.04.07
申请号 US20090574612 申请日期 2009.10.06
申请人 ALCATEL-LUCENT CANADA, INC. 发明人 KOKTAN TOBY
分类号 G06F12/08 主分类号 G06F12/08
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