| 摘要 |
An inverter 15 is configured by double gate TFTs 11 and 12, and an inverter 16 is configured by double gate TFTs 13 and 14. Top gate terminals of the TFTs that configure the inverter 15 are connected to an input terminal DAT(+), and bottom gate terminals are connected to an output of the inverter 16 and an output terminal OUT. Bottom gate terminals of the TFTs that configure the inverter 16 are connected to an input terminal DAT(-), and bottom gate terminals are connected to an output of the inverter 15. With this, threshold voltages of the inverters 15 and 16 are controlled so as to facilitate switching operations of the inverters, and whereby the comparator circuit 10 operates at a high speed. It is possible to obtain a comparator circuit that is insusceptible to a variation in the threshold voltages of the transistors and fluctuation of a common mode voltage of an input signal and capable of operating at a high speed.
|
