发明名称 Increasing effective transistor width in memory arrays with dual bitlines
摘要 A method for forming a memory structure, includes: forming an array of individual memory cells arranged in a network of bit lines and word lines, each individual memory cell further comprising a resistive memory device that is capable of being programmed to a plurality of resistance states, each of the resistive memory devices coupled to one of the bit lines at a first end thereof; configuring a rectifying element in series with each of the resistive memory devices at a second end thereof; configuring an access transistor associated with each of the individual memory cells, the access transistors activated by a signal applied to a corresponding one of the word lines, with each access transistor connected in series with a corresponding rectifying element; and forming a common connection configured to short neighboring rectifying devices together along a word line direction, in groups of two or more.
申请公布号 US7920406(B2) 申请公布日期 2011.04.05
申请号 US20080180586 申请日期 2008.07.28
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 BURR GEOFFREY W.;GOPALAKRISHNAN KAILASH
分类号 G11C11/00;G11C5/06 主分类号 G11C11/00
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