发明名称 |
Method and integrated circuits capable of saving layout areas |
摘要 |
An integrated circuit includes a diffusion layer, a first poly-silicon layer, and a second poly-silicon layer. The first poly-silicon layer is located on the diffusion layer to form a transistor. The second poly-silicon includes a first section and a second section. The first section of the second poly-silicon layer is located on the first poly-silicon layer to form a capacitor. The second section of the second poly-silicon layer is located on the diffusion layer to form a resistor.
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申请公布号 |
US7919821(B2) |
申请公布日期 |
2011.04.05 |
申请号 |
US20080100394 |
申请日期 |
2008.04.09 |
申请人 |
NOVATEK MICROELECTRONICS CORP. |
发明人 |
LI YAN-NAN;CHIANG HSUEH-LI |
分类号 |
H01L29/43;H01L29/49;H01L29/92 |
主分类号 |
H01L29/43 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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