| 摘要 |
A semiconductor memory cell array is disclosed which comprises an elongated continuous active region, a first transistor formed in the elongated continuous active region, the first transistor forming a first single-transistor memory cell, a second transistor also formed in the elongated continuous active region, the second transistor forming a second single-transistor memory cell and being the closest memory cell to the first single-transistor memory cell along the elongated direction, and an isolation gate formed on the elongated continuous active region between the first and second transistor, wherein the isolation gate has substantially the same structure as gates of the first and second transistor, and is supplied with a predetermined voltage to shut off any active current across a section of the elongated continuous active region beneath the isolation gate.
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