发明名称 ESD configuration for low parasitic capacitance I/O
摘要 An integrated circuit can include an I/O pad, an internal circuit, an inductor, an electrostatic discharge (ESD) protection circuit, and an ESD clamp. The internal circuit can be biased with a first voltage supply and a second voltage supply, where the internal circuit is connected to the I/O pad at a first node. The ESD protection circuit can be connected between the first node and a second node. The inductor can be connected between the second node and a third voltage supply. Further, the ESD clamp can be connected between the second node and the second voltage supply.
申请公布号 US7920366(B2) 申请公布日期 2011.04.05
申请号 US20090393417 申请日期 2009.02.26
申请人 BROADCOM CORPORATION 发明人 CHEN CHUN-YING;WOO AGNES NEVES
分类号 H02H9/00 主分类号 H02H9/00
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