发明名称 INTERCONNECTION DESIGN METHOD AND PROGRAM
摘要 PROBLEM TO BE SOLVED: To suppress change in a characteristic impedance of a signal, while minimizing the reduction of interconnectivity. SOLUTION: When a specific signal interconnection Wh adjacent to a via V is present, one end LP of an area ER where interconnectivity of interconnections including the specific signal interconnection is to be evaluated is made coincident with an edge line E4 opposed to the via V among edge lines E1 to E4 of the specific signal interconnection Wh, and then a value of an evaluation function is obtained. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2011065342(A) 申请公布日期 2011.03.31
申请号 JP20090214442 申请日期 2009.09.16
申请人 TOSHIBA CORP 发明人 NAKANO MIKIO
分类号 G06F17/50;H01L21/82;H01L23/12;H05K3/00;H05K3/46 主分类号 G06F17/50
代理机构 代理人
主权项
地址