| 摘要 |
PROBLEM TO BE SOLVED: To reduce parasitic capacitance between wirings in a peripheral circuit region of a semiconductor memory device. SOLUTION: The semiconductor memory device includes: the peripheral circuit region 40 with wiring layers 42, 46 having wiring patterns, a hollow 48 formed on an unwired region between wiring patterns in the wiring layer 42, 46, and an insulating film 49 forming at least part of a wall for demarcating the hollow 48; and a memory cell region 20. COPYRIGHT: (C)2011,JPO&INPIT
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